This invention relates to a circuit for generating two control signals. This circuit is particularly useful for generating control signals suitable for controlling the reading and writing of data into a static random access memory and for improving the performance of buffers.
Data supplied to a static random access memory (RAM) in a static RAM array is usually supplied on bit lines. The particular static RAM in the array into which the data on the bit lines is to be written is selected by word or select lines.
The bit lines are usually precharged; this means that the bit lines are caused to be in the high logic state (eg. 5 volts). Then when the data that is to be written into a static RAM cell are loaded onto the bit lines, one of the two bit lines is pulled low. In order to precharge the bit lines high before the loading of data, the bit lines should be precharged before the particular static RAM cell into which data is to be written is selected to prevent false data from being written.
The precharging of the bit lines is controlled by a precharge circuit and a precharge signal; the selection of the particular static RAM cell into which data is to be written or read is performed by setting the select line connected to such cell high (or low). After data has been written from the bit lines into the static RAM, the select line for the selected static RAM falls low (rises high) before the precharge circuit changes state in order to preserve the data already written into the static RAM.
The select signal on the select line and the precharge signal from the precharge circuit are derived from the same clock signal. However, in order to achieve the above effects, the precharge signal should have a fast rise time and a slow fall time compared to the clock signal and the select signal should have a slow rise time and a fast fall time in reference to the clock signal.
In conventional designs, precharge circuits have been used for controlling the bit line. However, such precharge circuits generate only a single control signal with a fast rise time and a slow fall time, but not the select signal with a slow rise time and a fast fall time. Therefore, another circuit will be needed to generate a select signal with a slow rise time and a fast fall time. It is therefore desirable to provide a control circuit of simple design which may be used to generate both types of signals.
A conventional CMOS output buffer includes a P-channel and a N-channel FET where the input signal to the buffer is applied to the gates of both transistors. One serious disadvantage of such conventional buffers is the large transient current generated by the buffer. For example, when the input signal rises from "0" to "1", during the transition period, the P-channel FET is not completely turned off when the N-channel FET begins to turn on. There is thus a transitional time period during which both FETs are turned on, which introduces large transient currents. It is therefore desirable to provide a control circuit for controlling the buffer in response to an input signal so that the changes in logic state in the input signal will not cause large transient currents to develop in the buffer.